Corresponding to the increased operating frequency and complexity of electronic devices, for example, with high-definition television (HDTV), there is a need for analog-to-digital converters (ADCs) to operate at higher sampling rates as well as provide greater conversion resolution. Typically, an ADC that is capable of operating at sufficiently high sampling rates must trade-off conversion resolution, while a high conversion resolution ADC usually is not capable of operating at high sampling rates.
A time-interleaved ADC (TI-ADC) array is commonly used when a single ADC is not capable of meeting the needed sampling rate while providing desired conversion resolution. A TI-ADC array comprises a plurality of ADCs arranged in parallel fashion with a signal to be converted being provided to each ADC in the plurality of ADCs. Each ADC is responsible for converting only a portion of the signal and therefore can perform the conversion at a slower rate. For example, if a TI-ADC array has M ADCs arranged in parallel fashion, where M is an integer number, then each of the M ADCs is only required to be able to convert the signal at 1/M-th of the desired sampling rate.
A problem that occurs in TI-ADC arrays, especially in arrays with a large number of ADCs, is that TI-ADC arrays are sensitive to non-uniform sampling mismatch distortion. The non-sampling mismatch distortion occurs when there are differences in the sampling times at the various ADCs in the TI-ADC array and presents itself in the form of frequency dependent aliases of the spectrum of the signal at integer multiples of the ADC sampling rate. These frequency dependent aliases degrade the signal to noise plus distortion ratio (SNDR) and the spurious free dynamic range (SFDR) of the ADC.
With reference now to FIG. 1, there is shown a diagram of a prior art implementation of a time-interleaved analog-to-digital converter (TI-ADC) array 100. The TI-ADC array 100 can be used where there is a need for high conversion frequencies as well as high conversion resolution, such as in digital television applications, i.e., high-definition television (HDTV). Rather than having a single high conversion rate, high resolution ADC that is capable of converting an analog signal at a sampling rate, fs, the TI-ADC array 100 makes use of a plurality of ADCs 105 arranged in a parallel configuration. The TI-ADC array 100, shown in FIG. 1, has a total of M ADCs 105. Each of the ADCs 105 may have a sampling rate of fs/M. Therefore, the sampling rate of the ADCs 105 can be significantly lower than the sampling rate of the overall TI-ADC array 100, fs. With the lower sampling rate, cheaper ADCs can be used, ADCs with a higher conversion resolution can be used, and/or the sampling rate of the overall TI-ADC array 100, fs, can be pushed higher.
An analog demultiplexer 110 can be used to provide an input signal, X(t), to inputs of the M ADCs 105. The analog demultiplexer 110 changes a coupling between the input signal, X(t), to an input of one of the M ADCs 105 at a frequency that is substantially equal to the sampling rate of the TI-ADC array 100, fs. For example, if the sampling frequency is 100 MHz, then once every 10 nano-seconds, the analog demultiplexer 110 changes a coupling between the input signal and an input to one of the M ADCs 105.
In order to meet the desired sampling rate of the TI-ADC array 100, fs, each of the M ADCs 105 needs to operate at a sampling rate of fs/M. Once every M*T seconds, wherein T is an inverse of the sampling frequency, fs, the analog demultiplexer 110 couples an input of an ADC 105 to the input signal, X(t). For example, with a sampling rate of 100 MHz and M equal to five, then once every 50 nano-seconds, the input signal, X(t), is provided to an input of an ADC 105. Each signal path containing an ADC 105 can be referred to as a channel.
A digital multiplexer 115 can be used to recombine outputs from the M ADCs 105 back into a single output signal stream, a digital signal stream made up of digitized samples of the input signal, X(t), represented as X(nT). The output signal, X(nT), comprises a sequence of digitized samples, one every T seconds, with a number of bits in each digitized sample being determined by the conversion resolution of the M ADCs 105. The digital multiplexer 115 changes a coupling between an output of one of the M ADCs 105 to the output signal at a frequency that is substantially equal to the sampling rate, fs. Therefore, an output of an ADC 105 is periodically coupled to the output signal once every M*T seconds.
The overall performance of a prior art TI-ADC array, such as the TI-ADC array 100 (FIG. 1), can be limited by sensitivity to offset, gain, and non-uniform sampling mismatches between the different ADCs 105. Offset mismatches, as in DC offset, between the ADCs 105 can contribute to a periodic additive pattern at the output of the TI-ADC array. In the frequency domain, this additive pattern appears as tones at integer multiples of the sampling rate of the uADCs 105, fs/M. Gain mismatches between the ADCs 105 result in spectral copies of the input signal to appear centered about integer multiples of the channel sampling rate (fs/2). Finally, non-uniform sampling mismatches produces frequency dependent aliases of the input spectrum at integer multiples of the channel sampling rate.
The non-uniform sampling mismatch of the array of FIG. 1 can be further decomposed into two components, a skew component and a clock jitter component. The skew component may be a result of propagation delays seen in a clock signal used to time the operation of the M ADCs 105 in the TI-ADC array 100. Due to differences in conductor trace length in the clock signal lines, mismatches between various active and passive devices, and so forth, a clock edge can arrive at each of the different M ADCs 105 at different times. This can lead to sampling time mismatches since the same clock edge at the different M ADCs 105 is assumed to be indicative of the same instance in time. The clock jitter component may be a result of inaccuracies in the clock generation circuitry.
Two-rank sampling is a known technique that can be used to help reduce the non-uniform sampling mismatch distortion. Two-rank sampling makes use of a front-end sampler operating at full sampling rate of the TI-ADC array to reduce any sampling time mismatches. Since a single full rate front-end sampler is used, sampling time mismatches at the various ADCs in the TI-ADC array can be minimized.
One disadvantage of the prior art approach is that there is a need for the front-end sampler to operate at the full sampling rate of the TI-ADC array. This circuit may be difficult to achieve in a size efficient and cost efficient manner. Furthermore, with the front-end sampler operating at full sampling rate, the TI-ADC array may have high power consumption. This can lead to heat dissipation problems as well as more stringent power supply specifications.